This application is a Continuation Application of application Ser. No. 10/329,503 filed Dec. 27, 2002, now U.S. Pat No. 7,148,863 which claims priority to Korean Patent Application No. 2001-86963 filed on Dec. 28, 2001, the subject matters of which are incorporated herewith.
1. Field of the Invention
This invention relates to a plasma display panel, and more particularly to a method and an apparatus of driving a plasma display panel that are adaptive for reducing an initialization period.
2. Description of the Related Art
Generally, a plasma display panel (PDP) allows an ultraviolet ray generated when an inactive gas such as He+Xe, Ne+Xe or He+Xe+Ne, etc. is discharged to radiate a phosphorus, to thereby display a picture. Such a PDP is easy to be made into a thin-film and large-dimension type. Moreover, the PDP provides a very improved picture quality owing to a recent technical development.
Referring to FIG. 1, a discharge cell of a three electrode AC discharge PDP includes a pair of sustain electrode having a scan electrode 30Y and a common sustain electrode 30Z formed on an upper substrate 10, and an address electrode 20X formed on a lower substrate 18 and crossing the pair of sustain electrodes. The scan electrode 30Y and the common sustain electrode 30Z have structures of transparent electrodes 12Y and 12Z and metal bus electrodes 13Y and 13Z being deposited respectively. There are an upper dielectric layer 14 and a Magnesium Oxide MgO passivation film 16 formed on the upper substrate 10 where the scan electrode 30Y and the common sustain electrode 30Z are formed side by side. On a lower substrate where the address electrode 20X is formed, there are a lower dielectric layer 22 and barrier ribs 24 formed and there is a phosphorus layer 26 spread on the surface of the lower dielectric layer 22 and the barrier ribs 24. There is inactive mixture gas such as He+Xe, Ne+Xe or He+Ne+Xe interposed into a discharge space provided between the upper/lower substrates 10 and 18 and the barrier ribs 24.
The PDP is driven with time-division by dividing one frame into various sub-fields that have different light-emission frequencies, so as to realize gray levels of a picture. Each sub-field is again divided into an initialization period for initializing the full screen, an address period for selecting scan lines and selecting cells from the selected scan lines, and a sustain period for realizing gray levels depending on a discharge frequency. For instance, when it is intended to display a picture of 256 gray levels, a frame period equal to 1/60 second (i.e. 16.67 msec), as in FIG. 2, is divided into 8 sub-fields SF1 to SF8. Each of the 8 sub-fields SF1 to SF8 is divided into the initialization period, the address period and the sustain period, as described above. The initialization period and the address period of each sub-field are equal for each sub-field, whereas the sustain period is increased at a ratio of 2n (wherein n=0, 1, 2, 3, 4, 5, 6 and 7) at each sub-field.
FIG. 3 shows a driving waveform of a PDP which are applied to two sub-fields.
In FIG. 3, Y represents a scan electrode, Z represents a common sustain electrode, and X represents an address electrode.
Referring to FIG. 3, the PDP is driven by dividing a frame into the initialization period for initializing a full screen, an address period for selecting cells and a sustain period for sustaining the discharge of the selected cells.
In the initialization period, there is a ramp-up waveform applied to all the scan electrodes Y simultaneously during a setup period SU. The ramp-up waveform causes a weak discharge within the cells of the full screen for wall charges to be generated within the cells. During a set down period SD, there is a ramp-down waveform applied to the scan electrodes Y simultaneously after the ramp-up waveform being applied, herein the ramp-down waveform falls down from a positive voltage lower than a peak voltage of the ramp-up waveform. The ramp-down waveform, as in FIG. 4, causes a weak erasure discharge within the cells, thereby uniformly leaving wall charges required for the address discharge within the cells of the full screen.
In the address period, a negative scan pulse SCAN is sequentially applied to the scan electrodes Y and, at the same time, a positive data pulse DATA is applied to the address electrodes X. While a voltage difference between the scan pulse SCAN and the data pulse DATA is added to the wall charges generated in the initialization period, an address discharge is generated within the cell supplied with the data pulse DATA. There are wall charges generated within the cells selected by the address discharge.
The common sustain electrode Z is supplied with a positive DC voltage Zdc during the set-down period and the address period.
During the sustain period, sustain pulses SUS are alternately applied to the scan electrodes Y and the common sustain electrodes Z. Whenever the sustain pulse SUS is applied, in the cell selected by the address discharge, wall voltages within the cell are added to the sustain pulse SUS to generate a sustain discharge in a surface discharge type between the scan electrode Y and the common sustain electrode Z. Lastly, after the completion of the sustain discharge, there is an erasure ramp waveform ERASE with a narrow pulse width applied to the common sustain electrode Z to make the wall charges within the cell eliminated.
By the way, the conventional PDP has a problem that the initialization period is excessively long because the gradient of the ramp waveforms RAMP-UP and RAMP-DOWN and the voltage variation range thereof are relatively big. Also, the conventional PDP has a problem that bias voltages of the ramp-up waveform and the ramp-down waveform fail to comply with address conditions. To describe in detail, for making the discharge property of the full screen uniform, if the gradients of the ramp waveforms RAMP-UP and RAMP-DOWN are set at a specified gradient and, as in FIG. 5, the bias voltage Vbias as a reference voltage at the point of time when the ramp-up waveform begins to be applied is the same as the bias voltage Vbias as a reference voltage at the point of time when the ramp-down waveform begins to be applied, the set-down period SD  is lengthened to be as long as the setup period SU. In this way, if the ramp-down waveform begin to be applied at the same voltage as the bias voltage Vbias of the ramp-up waveform, the weak discharge is kept relatively so long that the wall charges within the cell can be excessively eliminated. In this case, there is no address discharge generated because there is not enough wall charges accumulated within the cell to cause the address discharge even when the address voltage is applied.